Testing Logic Branch of Embedded Array Input Circuits With Limited Number of Inputs/Outputs
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18
An isolated array testing procedure when testing an embedded array on a logic chip has been known for some time. This approach fulfills the requirement of isolating the embedded array from the logic and testing the array, but the logic branch of all the array input circuits remains untested. It is very possible, therefore, that due to layout error or defects, the logic branch is defective even if the whole array is completely tested with the signal going through the test branch. This article discloses a means for testing the logic branch in an embedded array input circuit which cannot be tested through the normal isolation array testing procedure. Fig. 1 shows an embedded array on a logic chip. The isolation of the array from the logic is controlled by the control lines 1 and 2.