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Stabilizing Cascode Voltage Switch Logic

IP.com Disclosure Number: IPCOM000063500D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Miersch, EF [+details]

Abstract

An N-channel cascode tree is capable of providing any logic function conceivable with n inputs and 1 output which are each true and complement. Output nodes O, O are connected to supply voltage +V through P-channel load devices 1, 2 which, in turn, are connected to the precharge clock ECLK. Therefore, the double-ended cascode voltage switch (CVS) logic circuit operates in a clocked mode. However, certain input signal patterns may lead to a partial discharge, for example, of node O which is supposed to remain at 1 or +V in a given logic state. The partial discharge of node O is caused by this node, and thus its capacitance, being forced by the input pattern configuration to share the charge with some of the nodes in the N-channel cascode tree.