Browse Prior Art Database

Receiver for Clocked or Pseudo-Clocked Cascode Voltage Switch Logic

IP.com Disclosure Number: IPCOM000063506D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Miersch, E Wagner, O [+details]

Abstract

The receiver for a chip with clocked or pseudo-clocked cascode voltage switch (CVS) logic in CMOS technology must perform several functions: - converting TTL (transistor-transistor logic) levels into CMOS levels, - phase-splitting input signals to obtain complementary signals, - sampling and holding for synchronizing random input transitions for clocked logic, and - precharging receiver outputs to down level. The receiver shown in the drawing is suitable for these functions. Input signal IN is fed to the gate of a P-channel device T12, thus providing a high-ohmic impedance (no input currents). At the gate of a P-channel device T13, a reference voltage VREF (mean value of least positive up level and most positive down level of TTL) has to be supplied.