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Picocode Interrupt Mechanism

IP.com Disclosure Number: IPCOM000063517D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Pauporte, A Sazbon-Nathanson, D Thery, P [+details]

Abstract

Microprocessors use interrupt mechanisms in order to take into account external events as soon as they appear. This article relates to an interrupt mechanism which offers a hardware simplicity comparable to software-like interrupt mechanisms, is as fast as hardware-like interrupt mechanisms, and insures data integrity at any moment. The data consistency is insured by allowing the intervention of interrupts at safe states only. The external unit has direct access to a Central Control Unit (CCU) interrupt register (INT REG), where the interrupt origin is logged. At one moment, the interrupts allowed in the unique INT REG give the cause of the interrupt, and the picocode can directly branch to the processing of those interrupts, a starting address being associated with each cause in a software manner.