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Selectable Size Cache Array Disclosure Number: IPCOM000063538D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

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Brenza, JG [+details]


This article describes a generalized cache system organization that can easily accommodate a wide variety of cache sizes. The only modifications required to support this range of cache sizes are: (1) the physical population of cache chips in the package, and (2) some internal package wiring. No logic changes are required. The described caches are two-way set associative. Other set associativities (e.g., 4-way, 8-way, etc.) may be provided in a straight-forward manner. Fig. 1 shows three different interfaces from cache directory address selection logic to any one of three different size caches, each using the same line size of 64 bytes (i.e., 512 bit positions), and a 2X256X256=131, 072-bit position size chip.