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Lssd-Compatible Latch With Dual Independent Data/Clock Input Controls

IP.com Disclosure Number: IPCOM000063545D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Boudreaux, RP Crouse, RS Katz, NA [+details]

Abstract

A technique is described whereby a single latch circuit is used in place of a normally required two-circuit LSSD (Level Sensitive Scan Design) latch. The single latch circuit combines two stages of AND/OR/INVERT circuits to be controlled by two sets of input controls. This effectively reduces the logic overhead normally required to implement two LSSD latches, by using the equivalent logic of only one LSSD latch. During normal operation, +B clock tie-up 10, as shown in Fig. 1, and +C clock tie-up 11 are held active (+), and +A clock 12 and -A clock 13 are held inactive (-) and (+), respectively. During scan mode, the scan mode signal 14 will turn on (-), giving control of the +B 15 and -B 22 clock signals to the +B clock tie-up 10 input signal. At time A, as shown in Fig.