Browse Prior Art Database

SIGNAL VALIDITY DETECTION

IP.com Disclosure Number: IPCOM000063576D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Gavril, BD [+details]

Abstract

This article describes means for (a) establishing the validity of the output of flip-flops which "capture" asynchronous control signals and (b) preventing the use of any such output when it is likely to be invalid. The means described herein provide 100% validity of circuit output, i.e., 100% reliability. This scheme has been applied to the logical specification of the Interface Control Unit (ICU) portion of the IBM Micro (m)/370 microprocessor, a single-chip NMOS microprocessor conceived and designed at the T. J. Watson Research Center. The ICU is one of two logically distinct portions of m/370 the other being the microprocessing unit (MPU). The MPU resides in the "interior" of the chip and is concerned primarily with instruction processing.