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Error Checking for a Full CARRY Look-Ahead Adder

IP.com Disclosure Number: IPCOM000063604D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Hallman, SA [+details]

Abstract

This technique provides 100% error checking of a carry lookahead adder. HALF SUM CHECK The sum of an adder is often generated by the EXCLUSIVE OR of the half sum with the carry in. From the half sums, a half sum check can be used to check for possible one-bit failures. This check can be very effective if the half sums are created in the proper form (Shown Below). The check is implemented by EXCLUSIVE ORing all the half sum bits together with the parity of both operands being added, resulting in a value of zero for a non-error state. Hcheck=Pa V Pb V Hn V Hn-1 V -H1 V HO where H = half sum. This check will find any single bit errors in the value of the operands coming into the adder or any error in the half sum circuitry. However, the way in which the half sum is generated is very important.