Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18
A method is defined herein for "re-embedding" a logic design into a portion of a chip, module, or board. Its function is to map a redesign of the logic of the hardware which had been critical with respect to timing. A form of logic optimization for delay reduction is used in a prior process and, to the extent that it is possible, to minimize the logic. In this re-embedding process, both timing and space are critical; strategies are used to deal with these constraints. Timing verification was used extensively -- several different procedures used -- in the design of the processor complex, for commercially available computers. The correction, however, consisting of a redesign of the "critical" hardware, was performed manually, an arduous process.