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Deferred Decoding

IP.com Disclosure Number: IPCOM000063610D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Pomerene, JH Puzak, TR Rechtschaffen, RN Sparacio, FJ [+details]

Abstract

A modified address generating procedure enables the instruction unit temporarily to put aside those instructions that cannot be immediately executed because of logical or physical interlocks, one of which is address generation interlock (AGI), and advances the program execution to succeeding instructions which are not dependent upon the bypassed instructions, thus greatly reducing the delay that otherwise would be encountered in waiting for execution of the bypassed instructions. The following sequence of IBM System/370 instructions will be considered as an example: A. LD GPR(4) FROM MEMORY USING GPR(6) AS BASE B. LD GPR(4) FROM MEMORY USING GPR(4) AS BASE C. LD AND TEST (LTR) GPR(4) AND SET COND. CODE D. BRANCH ON COND. (BC) USING GPR(10) AS BASE E. "AND IMM.