Browse Prior Art Database

Multi-Line Gateway Controller

IP.com Disclosure Number: IPCOM000063615D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Johnson, WJ Maxwell, HM Millas, RJ Weakley, TL [+details]

Abstract

A technique is described whereby a multi-line gateway controller is used to off-load the main central processing unit (CPU) when performing gateway functions. In data communications, a gateway is a device in which data is received in one protocol and retransmitted in a different protocol. Therefore, a gateway permits two devices communicating in different protocols to communicate with each other. The multi-line gateway controller, as shown in the figure, consists of universal synchronous/ asynchronous receiver/transmitter (Usart) modules 10, microprocessors 11 for controlling the communications on the line, random-access memory (RAM) modules 12 containing the microcode protocol, read-only memory (ROM) 13 containing the diagnostics and down-load program and the multi-line bus isolator 14.