Overlapping Instruction Unit Delay With Instruction Prefetching
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18
In many high performance pipelined machines, the occurrence of certain conditions causes the Instruction (I) Unit to stop until the condition is cleared, e.g., Address Generation Interlocks, Queue Full condition, All Operand Address Registers busy condition, etc. In some of these situations the opportunity exists for prefetching the target stream of a branch instruction: L 4, 8(6) L 5, 16(4) BC F, 80(6). If the target stream is prefetched, then two potential benefits accrue when the I Unit eventually continues. 1) The BC and the target instruction can be decoded on successive cycles, thereby eliminating the taken branch delay. 2) The additional opportunity for instruction fetching can reduce the delay due to Empty I Buffer.