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Signal Equivalence Gate

IP.com Disclosure Number: IPCOM000063634D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Klambatsen, PH Levi, R Zalph, WN [+details]

Abstract

A technique is described whereby AND/OR gate equivalence circuits are analyzed in accordance with the Karnaugh Map for equivalence circuits, and a concept circuit using NMOS enhancement technology is discussed, so as to provide the minimum number of transistors, as related to the number of inputs in AND/OR gate circuits. A typical implementation of an AND/OR gate circuit, as shown in Fig. 1a, shows how inputs A, B, C and D would produce output X. Fig. 1b shows the Karnaugh map for this circuit. Alternative equivalence circuits are shown in Figs. 1c and 1d. The relationship of the number of transistors required in the two circuits, as a function of the number of inputs, is shown in the graph (Fig. 2). It should be noted that logically implemented in AND/OR blocks, the alternative circuit of Fig.