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In-Line Serial Parity Checker for Serial and Parallel Data Disclosure Number: IPCOM000063635D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

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Parish, SW [+details]


An "in-line serial parity" checker is shown in Fig. 1 for serial data and in Fig. 2 for parallel data. The top and bottom circuits of Fig. 1 are used as traditional parity checkers checking either even or odd parity. Setting or resetting the flip-flop 10 prior to running the test allows for testing of even or odd parity, respectively. Resetting the parity latch (flip-flop) results in an output of 1 for odd parity as correct parity and an output of 0 for even parity as correct parity. Stated differently, for odd parity an output of a 1 is correct and a 0 is an error. On the other hand, for even parity, an output of a 1 is an error and of a 0 is correct. The circuit of Fig. 2, when used in a system such as shown in Fig. 3, more completely tests the data path hardware by including the shift register 11. If memory 12 in Fig.