Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18
This article relates to an increasing interest in means for 'on-chip' failure testing for VLSI. The methods proposed thus far are basically variations on the following scheme. 'Pseudo-random' tests are generated on-chip by some type of feedback shift register. These tests are not constructed to detect any particular assemblage of failures. Enough of them are generated, i.e., 10,000,000, so that the 'probability' of 'failure coverage', always computed for 'stuck' failure alone, is adjudged sufficiently high. On the chip, the results of applying such a large number of tests are correlated by 'signature-register analysis', to detect, with some probability, the occurrence of a failure. Recent designs show a substantial 'overhead', the fraction of the chip devoted to the selftest mechanization itself, from 18% to 77%.