Modified Error Correction Code Design to Allow Partial Word Writing to Memory Locations Which Contain Double Bit Errors
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18
A technique is described whereby microprocessor systems using error correction codes (ECCs) are modified so as to allow partial words to be written into memory locations which contain double bit errors. The concept combines parity and ECC detection logic to allow bytes to be written to a memory location that has implemented ECC controls on word boundaries and is done without masking out errors in the unwritten half of the word. In microprocessor systems, such as the IBM Series/1, which use a 16-bit data word but only 6-bit error correction code, the instruction set includes a number of byte operations that have the capability of writing and reading bytes from memory. To execute a byte read/write cycle, the whole word is read from memory and the unused half is discarded.