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Self-Aligned Polycide Base Contact for Bipolar Transistors

IP.com Disclosure Number: IPCOM000063642D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Stork, JM Tang, DD [+details]

Abstract

This article relates generally to a method for fabricating bipolar semiconductor devices and more particularly to a method for forming a self-aligned silicide base contact by the evaporation of silicide. Still more particularly it relates to a method which provides a low resistance base contact and interconnect which enables accurate control of link-up. Fig. 1 shows a cross-sectional view of a bipolar transistor at an intermediate stage of fabrication. Standard bipolar technology is used to provide an isolated bipolar device region 1 in n-epi layer 2 formed on an n+ subcollector layer 3. Thin layers 4,5 of SiO2 and Si3N4, respectively, are deposited and patterned to define the emitter width, as shown in Fig. 1, which is therefore very tightly controlled.