Browse Prior Art Database

Global Planarization by Laser Etching

IP.com Disclosure Number: IPCOM000063648D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Aliotta, CF Clarke, TC Donelon, JJ Tomkiewicz, Y Tong, HM Yeh, JT [+details]

Abstract

This is an efficient method of achieving uniform polymer coatings on substrates containing non-uniform trench distributions in packaging of LSI (large-scale integration) chips. Deep dielectric isolation of adjacent semiconductor devices in chip fabrication requires the presence of intervening trenches filled with a material of low dielectric constant, typically a polyimide. Device requirements may lead to a non-uniform distribution of these trenches within a given chip. Thus, in some locations these trenches, on the order of two microns wide and five microns deep, may be separated by as little as three microns. In other regions, however, adjacent trenches may be as far as several mils apart.