Common Substrate Design for Wirebonded/Hermetic VLSI Devices
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18
This article describes a common multilayer ceramic (MLC) substrate, for the packaging of a VLSI semiconductor chip, of the type having, e.g., four ceramic layers bonded together to form a substrate with a cavity in which the chip resides. The common configuration enables reduction of the number of metal layers to a single layer, provides commonality of tooling for substrate manufacture and component assembly, and is applicable to a "family" of sizes and types. Referring to the figure, a partial cross section of a four-layer substrate C1-C4 having a device 12 in place is shown electrically connected to the plated substrate wires 14 by way of a "step"-type wirebond 16, as is known.