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Battery Backup Circuit for CMOS RAM

IP.com Disclosure Number: IPCOM000063660D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Nishio, T [+details]

Abstract

This article describes a battery backup circuit for a CMOS RAM. Normally, a voltage applied to the CMOS RAM is maintained to be substantially equal to a system supply voltage. When the system supply voltage goes down, a battery supplies power to the CMOS RAM to retain data. Referring to the figure, the circuit includes a battery V1 which provides +3.0 volts (DC), for example. On the other hand, a system supplies a voltage VCC which is +5 volts and a voltage VCC 2 which is 12 volts, for example. Normally, a transistor Q2 is in its on state, and a voltage VDD applied to the CMOS RAM is maintained to be substantially equal to the VCC by arrangements comprising a transistor Q1, resistors R1 and R2, and diodes D1 and D2.