Browse Prior Art Database

Address Mapping for a Memory System With a Prime Number of Banks

IP.com Disclosure Number: IPCOM000063661D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Mirza, JH White, SW [+details]

Abstract

Many large scientific and engineering computers currently have multiple memory banks to reduce memory conflicts and decrease the average memory access time. Generally the number of banks is chosen to be a power of two to simplify the mapping of an address onto a memory module. However, the advantage of multiple memory banks is lost when consecutive accesses are to the same module. For example, when accessing along a row of an array that is stored in column major order, the stride can be a multiple (or a submultiple) of the number of memory modules. In such a case, the processor's performance is noticeably degraded. Several recent multiprocessor systems propose using a prime number of memory modules to allow conflict-free access along multiple directions within an array.