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Chip-Enable Circuit for Battery Backup CMOS RAM

IP.com Disclosure Number: IPCOM000063667D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Nishio, T Seki, Y [+details]

Abstract

The present circuit functions to maintain a chip-enable (+CE) terminal of a CMOS RAM at a low voltage level to minimize power dissipation while the CMOS RAM is used in a battery backup (retention) mode during a power down time. The CMOS RAM shown in the figure receives a voltage VDD which is normally derived from a system supply voltage VCC through a battery backup circuit. The VCC is +5 volts, for example. In the normal situation, a high-level signal voltage is applied to the CE terminal of the CMOS RAM, since a conventional power-down detector maintains its output at zero level to keep a transistor TR in its on state. When the VCC drops, the power-down detector raises its output to a high level if the VCC becomes lower than a threshold, e.g., +4.75 volts, thereby turning the transistor TR off.