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Organelle for Logically Growable Data Spaces

IP.com Disclosure Number: IPCOM000063674D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Moore, VS Thoma, NG [+details]

Abstract

A technique is described whereby a dynamic latch and a static latch in shift register logic (SRL) technology provide a basic organelle for use in a wide application of logic circuits. The circuit structure features multiple input and multiple output capabilities to provide growable data spaces. The circuit, as shown in the figure, incorporates transistor circuits T1 to T5 which form an input multiplexer, physically configured to read data from one of five data sources. Transistor 24 is used for testing purposes. T6 to T10 form an output multiplexer that can write data to one of five data busses. T8 and T9, although not shown, are implied to be part of the circuit. Depletion capacitor 11, tied to the input gate of T21, forms a data inverter in conjunction with T22.