Browse Prior Art Database

Partially Good Chip Part Number Reduction by Dynamic Relocation Disclosure Number: IPCOM000063675D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue


Related People

Anderson, KL Ellenberger, AR Ellis, WF Streck, JP [+details]


All partially good chips are made to appear "bad" in an identical memory location by incorporating address translation (permutation) logic and fault location memory to all chips. The chips can then be treated as a single part number, regardless of varying physical fault location. This is accomplished by incorporating a spare location or address in the memory array. The address translation logic redirects any signal addressed to the bad location into the spare, as schematically shown in Fig. 1. An address of the chip is designated as a "spare" location, e.g., address Z in the array partition of N sections, as shown in Fig. 2. Address Z is to be the logical bad address for all partial chips. The Address Location Logic (that which selects 1 of N) transforms a bad location address, X, to spare address, Z.