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Dual Purpose Use of TLB Registers

IP.com Disclosure Number: IPCOM000063685D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Boguski, MJ Callahan, RW Oliver, BL [+details]

Abstract

This article describes the dual purpose use of translation look-aside buffer (TLB) registers that eliminate the need for an address register, which is normally used only to store the current address during an error condition. The TLB real registers are used as dual purpose registers. During an error condition, the entire virtual address bus 11 is latched in the virtual 12 and real 13 registers that the least recently used (LRU) is pointing at. The failing address can then be read by using the LRU to gate the TLB registers, which contained the error address, onto the data bus 14. The TLB entry is updated by just writing into the real register 13, since the virtual register 12 already contains the updated address that was latched during the previous error condition, such as a TLB miss.