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Programmable Address Inverting Circuit

IP.com Disclosure Number: IPCOM000063686D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Scheuerlein, RE [+details]

Abstract

This circuit provides selected switchable complementary output signals which drive an address buffer. This is useful in the implementation of a dynamic relocation strategy to minimize part numbers of partially good chips. The relocation strategy is essentially to assure that, regardless of the original fault location, its initial address is always transformed to a predetermined address. The circuit shown in the figure provides the ability to invert the buffer drive signals by blowing the fuse, thus transforming the initial address to the predetermined location in the buffer. Circuit operation is as follows: to start the address trapping clock (ASR) or sensing clock for the address buffer, ASR rises and unconditionally forces both Gate 1 and Gate 2 to ground.