Browse Prior Art Database

Processor Unit MASK Generation Control

IP.com Disclosure Number: IPCOM000063688D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Cannon, JW Finney, DW Rave, WC [+details]

Abstract

The Arithmetic Logic Unit (ALU) of a processor unit contains mask generation logic, shown in the drawing, which is utilized to build a 32- bit mask string. There are six modes of mask formation. The 32-bit mask is always generated, but is used only when a control, referred to as merge control, is active. During the execute cycle of the processor unit, an 11-bit mask control field (Bits 21-31 of B control register) defines the mask to be generated. This logic builds a 32-bit mask string of either ones surrounded by zeroes or zeroes surrounded by ones. In a representative architecture, there are four instructions (M-FORM) which provide the 11-bit mask field to perform their function.