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High Speed Hi-Pot Stress Test

IP.com Disclosure Number: IPCOM000063690D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Brzozowski, WA [+details]

Abstract

A hi-pot testing procedure that can simultaneously test multiple nets in a complex card, board or a substrate, that normally require a long dwell time, speeds up the test by employing a shuffle pattern. Electric fields are produced in the component by placing a selected voltage at one net on the substrate, card, or board, and by grounding the others. This step is repeated for each net so that every portion of the component is at some time subjected to the maximum field strength possible for the associated voltage. This is represented symbolically in Table 1, with a 1 representing the voltage and 0 representing ground. For simplicity, an 8-net component is shown: (Image Omitted) Note that if there are N nets that there will be N tests.