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Parallel-Array Incrementing Network

IP.com Disclosure Number: IPCOM000063699D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Ling, DT Matick, RE [+details]

Abstract

In general-purpose and special-purpose processors, there is often a need for an "increment" function which essentially adds 1 or 0 to a number loaded in a register. This is typically done with a simple "carry-propagate" adder circuit shown schematically in Fig. 1. For such a case, the "carry" must propagate from the lowest-order bit A0 (or B0) to the highest-order bit An-1 (or Bn-1). Thus, at least n stages of delay will be needed before the carry is available to determine the final high-order sum bit Bn . Many circuits have been proposed to circumvent or minimize this carry delay problem using standard logic gates, i.e., ANDs, NORs, NANDs, etc.