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Multiple Caches to Increase Cache Bandwidth Predicated on Congruence Class Disclosure Number: IPCOM000063740D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

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Pomerene, JH Puzak, TR Rechtschaffen, RN So, K Sparacio, FJ Villani, RD [+details]


In a high performance uniprocessor that has pipelining and out of sequence execution, the demands of the processor on the cache for fetches or stores will often exceed one fetch or store per machine cycle. Even assuming only one decode per cycle, a method of alleviating this problem is to split the cache into "N" caches (N=2 is probably the most useful and cost efficient) predicated upon congruence classes within the cache. Thus, for N=2, all odd congruence classes would be in one cache and all even congruence classes would be in the second cache. The DLATs (Dynamic Look-Aside Tables) used to translate virtual addresses to real addresses would be duplicated to allow simultaneous access to both caches, and there would be two directories, one for even, one for odd, congruence classes.