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Optimized Lssd-Compatible Synchronous Binary Decrementer With Timer Capabilities Utilizing L2* Latches

IP.com Disclosure Number: IPCOM000063751D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Baker, ED Boudreaux, RP Crouse, RS Katz, N [+details]

Abstract

A technique is described whereby a synchronous binary decrementer is used as a byte counter and is decremented for each byte of data transferred. Since the decrement function is important in the control of data flow implementation, this design requires minimal logic overhead while adhering to Level Sensitive Scan Design (LSSD) ground-rules. Also, described is how the synchronous binary decrementer may be utilized as a timer, to determine specific time intervals. The L2* (second stage) latches are parallel loaded from +Data Bus Bits and Load L2* C Clks 11 and 12, as shown in Fig. 1. The byte Counter-Shift (shown as two bits wide) is then decremented by a logically generated signal from +Step Cntr 13. -Allow timer 14 and -Byte Cntr 15 are both off.