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Polarity Hold Latch With Tristate Output

IP.com Disclosure Number: IPCOM000063754D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Cases, M Kraft, WR [+details]

Abstract

A technique is described whereby a tristate polarity hold (PH) latch is implemented to provide a tristate gate array family. The concept uses a standard PH latch transmission gate approach with buffered outputs to provide a gate array with no stability feedback sensitivity and a minimum number of devices and input control signals. The tristate PH latch circuit, as shown in Fig. 1, allows data to flow when transmission gate 10 opens and transmission gate 11 is closed through inverter stages 12 and 13 through buffers 14 and 15 to the load. Actual latching occurs when transmission gate 10 is closed and 11 is open allowing the output from inverter 13 to feedback data in phase to the input. The polarities of the gate inputs to the transmission gates must be correct to insure proper feedback and isolation.