Improved Adjacent Cell Disturb Measurement Technique
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18
As shown in Fig. 1, cells connected to WL2 written to zero can leak or be coupled improperly to a lower than desired voltage. This could result in leakage through the I/O device to the bit line which will disturb "ones" read from an adjacent cell connected to WL1. An improved adjacent cell disturb measurement technique allows accurate measurement of a zero's lower than desired voltage level by preventing early spill of that voltage onto the bit line. Between the time the cell is written to a zero state and the time the effects of any lower than desired voltage level for the zero are detected, the voltage on the line PL1, connected to the memory cell capacitor, could fall in intervening memory cycles and change the lower than desired voltage level of the zero.