Port-Multiplexed Register File
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18
In known multiport register file memories, any word in the array may be written into, or read out of, a multiplicity of separate accesses. The known art multiplexed performance by first writing and then reading once every cycle. For each read port a separate true/complement generator set, word decoder bank and drivers were provided. All writes occurred simultaneously, and then all reads occurred simultaneously, establishing the need for as many accesses, or "bit line pairs," to the cells as there were read or write ports, whichever greater. This scheme takes advantage of the speed found in hardware built in the prior art's architecture. A register array with only two accesses is used, and the architecture multiplexes for the number of ports rather than to function.