Browse Prior Art Database

Release of Latch-Up Current

IP.com Disclosure Number: IPCOM000063761D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Matino, H [+details]

Abstract

This article relates generally to large-scale integration of circuits and more particularly to a method of preventing current latch-up in the circuits due to extraneous signals. Destructive current latch-up of CMOS integrated circuits, that is, conduction continuing after termination of an internal or external noise signal, can be prevented by back-biasing the substrate. Although current latch-up can be prevented by maintaining transistor current gains of less than unity or limiting maximum holding current, the higher circuit densities with submicron dimensions do not permit these techniques. An integrated circuit configuration having latch-up tendency translates from the actual embodiment of an N well in a P substrate in Fig. 1a into the schematic parasitic PNPN switch circuit of Fig. 1b.