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Improved Approach to the Use of Booth's Multiplication Algorithm

IP.com Disclosure Number: IPCOM000063781D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Rodriguez, JR [+details]

Abstract

A technique is described whereby the Booth method of multiplication is improved when using multiples of the multiplicand to generate a partial product. The concept reduces the total number of initial cycles necessary to form the multiples and reduces the number of registers required to hold the values in the multiplicand. This is a distinct advantage whenever three or more bits of the multiplier are used to generate the multiplicand multiples. Therefore, a multiple reduction technique is used in the formation of the multiplicand multiples, thereby reducing the number of inputs to the adder input multiplexer. For the typical implementation of the Booth algorithm for multiplication with two-bit shifts, as shown in the data path of Fig. 1, the multiplicand is held in B-register 10.