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Self-Clocked Cache Disclosure Number: IPCOM000063782D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

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Matick, RE [+details]


Clock generation and distribution are serious problems in computing systems. Self-timing circuits on the same chip have a distinct advantage because they track with circuit-speed variations, but generation of on-chip clocks usually is complex and expensive. A simple modification to the translation lookaside buffer (TLB) and cache directory macros is described that provides an on-chip generated clock for use in a serial-access one-cycle cache. Such a clocking feature is essential in most systems that use only two clocks, one at the start and one at the end of the CPU cycle. However, self-clocking is highly advantageous even if other global clocks are available since it eliminates timing skew problems and allows fast chips to run at a smaller critical path delay. Thus, sorting of fast chips for fast systems is possible.