Browse Prior Art Database

Three Dual Polysilicon Gate CMOS With Diffusion Barriers and the Process for Forming Each

IP.com Disclosure Number: IPCOM000063789D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Chao, HH Taur, Y Ting, CY Wang, LK [+details]

Abstract

Three types of submicron complementary metal-oxide semiconductor (CMOS) devices and the process for forming each type are disclosed in this article. Procedures for fabricating dual polysilicon-gate field-effect transistors (FETs) with diffusion barrier material that blocks diffusion and preserves transistor threshold voltage above both the N-type and P-type gates, the N gate only, and the P gate only are described. The diffusion barrier layer is placed between the polysilicon gates and a silicide overlayer, the latter of which acts as a shunt conductor. In submicron technology, buried channel devices are susceptible to problems caused by increased processing temperatures. Transistors with dual polysilicon gates with a silicide overlay have been found useful in alleviating this problem in CMOS applications.