Interconnection Method for Testing VLSI Semiconductor Wafers
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18
A technique is described whereby an improvement in probe card interconnection methods, used in the testing of very large-scale integrated (VLSI) semiconductor wafers, is implemented so as to increase reliability and reduce costs. Prior art required custom hand-made coaxial cables soldered and individually checked in order to provide reliable high-frequency testing of VLSI components. The connector pin spacing of the probe card was only .050", causing soldering difficulties and precluded the use of any insulation, displacement force, mass termination connectors. The concept implemented to overcome the high cost of custom-made interconnection devices was to redesign the probe card so as to utilize both side edges of the card. This enabled the connector pin spacing to double, to .