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Dynamic RAM Cell With Merged Drain and Storage

IP.com Disclosure Number: IPCOM000063803D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Chin, D Lu, NC Nguyen, TN Ning, TH [+details]

Abstract

This article relates generally to the fabrication of integrated circuits and more particularly to the construction of a dynamic random- access memory cell requiring less space. A one-transistor dynamic RAM cell requiring less surface area is constructed by burying the cell storage capacitor beneath the drain. This cell is shown in Fig. 1 and needs only three minimum feature-sizes in length for the active area. The drain and storage node are connected by a buried vertical layer contact formed during an added step of photoresist planarization. The known deep trench capacitor is used, but in an inverted manner, in which polysilicon forms the storage node and the substrate forms the counter-electrode.