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Single/Block Transfer Mode Design Combination for DMA Controllers and Central Processing Units Using a Uniform I/O Protocol

IP.com Disclosure Number: IPCOM000063804D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Miranda-Portillo, JB [+details]

Abstract

A technique is described whereby single transfer direct memory access (DMA) operation mode is designed to be operational with DMA controllers, such as the Intel Corporation i8237A, i8237A-4, i8237A-5 and any Intel CPU which uses a uniform input/output (I/O) protocol. The concept enables the controller to perform block I/O transfers with greater integrity than presently available in block transfer mode. It provides, in single transfer mode, a handshake synchronization capability on individual bytes without increasing timing overhead. The need for operating a DMA controller in a single transfer mode is particularly useful in order to maintain data transfer integrity between the CPU system memory and intelligent I/O devices, or vice versa.