Browse Prior Art Database

Prevention of Latch-Up Current

IP.com Disclosure Number: IPCOM000063819D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Matino, H Ning, TH [+details]

Abstract

This article relates generally to integrated circuit structure and more particularly to a technique of preventing current latch-up in CMOS circuits due to extraneous signals. In CMOS integrated circuits, either external or internal noise pulses can cause current conduction that continues after termination of the pulses. This eventually burns out the circuit. By connecting contact metal to only the emitter of the parasitic transistor, through a heavily doped p+-n+ tunnel diode, a reverse bias is developed in response to the latch-up current and thereby terminates the latch-up conditions. Referring to the integrated structure of Fig. 1 and its equivalent circuit in Fig. 2, the contact metal, connected to supply Vdd, is connected only to the n+ contact in conventional n-well CMOS.