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Diagonal Layout of Gate Array

IP.com Disclosure Number: IPCOM000063823D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Feth, GC [+details]

Abstract

This article relates generally to the fabrication of integrated circuits and, more particularly, to the arrangement of logic gates in very large-scale integration. When logic gates are laid out diagonally with respect to overlying rows and columns of wiring tracks that are mutually orthogonal, the gates have improved accessibility, require smaller areas, and permit less parasitic wiring capacitance. Referring to the figure, gates 1 are located in essentially rhomboidal regions 2 between voltage and ground buses 3 and 4 that are implemented in first level metal and run vertically. Gates 1 are composed of one or more islands 2 of conductive p+ polysilicon or silicide. Islands 2 contact the external bases of upward-injecting npn transistors.