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High-Density Cell Layout Design for VLSI Semiconductor Chips Disclosure Number: IPCOM000063829D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

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Feth, GC Mikhail, WF Weiss, L [+details]


This article relates to the design of very large-scale integration (VLSI) semiconductor chips, and more particularly to a high density cell layout design for such chips. In this article a new layout design for integrated-circuit cells is described which provides more LSTs (logic service terminals) and increased flexibility in the locations and uses of LSTs than are available with existing designs. The new design offers improved wirability as well as increased density of gates in master-slice and/or master-image layouts. The great flexibility in accessing the LSTs of the cells is exemplified by the fact that all wiring tracks which connect to an output LST of a gate can connect to an input of another gate using but a single wiring track in either the X or the Y direction. An example of a cell 1 is shown in the figure.