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Clocked Differential Cascode Voltage Switch Logic Circuit Disclosure Number: IPCOM000063848D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

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Meyers, RF [+details]


A method is described to eliminate charge-sharing problems occurring during the operation of clocked differential cascode voltage switch (CVS) logic circuits. A differential CVS logic circuit in CMOS technology comprises a tree of N devices connected in current switches, as indicated in the dotted part of the drawing. This tree is designed to perform logic functions and has true/ complement logic inputs A and B and a logic output at nodes 1 and 2, connected to true/complement output nodes O and -O, respectively, through buffers T4, T5 and T6, T7. Each buffer contains a feedback device T8, T9. This CVS logic circuit is a dynamic logic circuit with a precharge and a signal propagation phase. Nodes 1 and 2, the buffer input nodes, and tree internal nodes 4 and 5 are precharged and restored by P devices T1, T2 and N device T3.