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Noise Immunity Improvement of CMOS-CVS Logic Circuits Disclosure Number: IPCOM000063855D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

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Boertzel, MW Miersch, EF Wagner, OM [+details]


The noise immunity of CMOS-CVS (cascode voltage switch) logic circuits is improved by adding a bipolar diode series-connected to the FET path. This raises the noise immunity level of a threshold voltage by the forward voltage drop of the diode. The thus reduced voltage swing is then amplified to a voltage swing at the output buffer. The most critical noise limit for the functionality of CMOS-CVS logic circuits is determined by the differential noise limit at the input of the N-channel devices. The limiting factor is the N-channel threshold voltage. VLSI chips normally generate high chip internal noise, so that such limitation leads to a marked deterioration of performance.