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Guard Ring Connection in CMOS Structures

IP.com Disclosure Number: IPCOM000063862D
Original Publication Date: 1985-Apr-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Hanafi, H Ludwig, T Schettler, H Wagner, O [+details]

Abstract

The complementary transistors of structures integrated on a semiconductor chip in CMOS technology are separated from each other by a guard ring zone to avoid the known latch-up problem. The purpose of the guard ring is to collect electrons which are emitted by forward-biased NP junctions of the N transistors in response to undershoots and line-to-line coupling. The emitted electrons would lead to an uncontrolled substrate current. As such a current, when passing the P transistor area, may cause a latch-up effect, an N well guard ring is used. The problem inherent in the guard ring is how to connect it to the power supply VH.