Browse Prior Art Database

Device-Isolation Technique

IP.com Disclosure Number: IPCOM000063883D
Original Publication Date: 1985-May-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Saretto, S [+details]

Abstract

A process is disclosed for forming field-effect transistor devices in a layer of polycrystalline silicon so that the device areas are surrounded by a field region of high resistivity of polycrystalline silicon. The process starts by depositing a layer of polycrystalline silicon on a monocrystalline silicon substrate by means of a chemical vapor deposition technique, so as to form a five-micron-thick layer of polycrystalline silicon. The process continues with the focusing of a laser beam on the intended device areas of the polycrystalline silicon layer so that heating of the regions can be carried out to recrystallize the polycrystalline silicon layer thus exposed. The object of the laser heating is to anneal the polycrystalline silicon layer in the limited area intended for the field-effect transistor device.