Browse Prior Art Database

Frequency/Phase Detector

IP.com Disclosure Number: IPCOM000063941D
Original Publication Date: 1985-May-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Jorgenson, GW [+details]

Abstract

Phase detectors of the 180-degree sawtooth type are commonly used for reading encoded data channels. Capture range and false lock are problems associated with this type of detector. The use of a frequency/ phase detector logic, as described below, improves the capture range (with no hokey lock) of the PLL (phase-locked loop) design without degradation in reading the encoded data. Fig. 1 shows the basic block diagram of a PLL consisting of four major sections: detector 10, charge pump 12, filter 14, and voltage-controlled oscillator (VCO) 16. The detector compares the incoming encoded logic signal 'PDATA' with the generated clock signal 'CLOCK'. The error between the two results in charge up 'CHG UP' or charge down 'CHG DWN' logic signals.