High Performance Variable-Length Message Interface
Original Publication Date: 1985-May-01
Included in the Prior Art Database: 2005-Feb-18
An arrangement is disclosed to improve the communication protocol between an IBM Series 1 processor and the automated equipment employed for inserting components onto a circuit card. The arrangement employs the EXIO command of the Series 1 processor to initiate the chain of cycle steal Data Control Blocks (DCBs) shown in the figure. This avoids dedicating the Series 1 (S/1) processor for handling each byte of data being transferred. The first pair of DCBs allow the writing of process commands to the insertion equipment. The pre-receive function of DCB 1 permits the adapter to switch from write mode to receive mode much faster. DCB 2 directs the adapter to receive one byte of data which is normally an acknowledgement (ACK) or no acknowledgement (NAK) character.